VHDL Forum's Journal|
[Most Recent Entries]
Below are the 19 most recent journal entries recorded in
VHDL Forum's LiveJournal:
|Saturday, May 4th, 2013|
|Thursday, May 11th, 2006|
new entity !
Hi buddies !
I have just joined this VHDL community. I am sure there are many interesting VHDL concepts we all can share among us. Current Mood: energetic
|Wednesday, April 19th, 2006|
Flat verilog netlist
May be it's a dumb question but ... =)
I have a hierarchical Verilog, something like that:
module slice (in1, in2, in3, out1, out2);
input in1, in2, in3;
output out1, out2;
nand2 gate1 (in1, in2, out1);
nand2 gate2 (in2, in3, out2);
module c17 (n1, n2, n3, n4, n5, n10, n11 );
input n1, n2, n3, n4, n5;
output n10, n11;
slice s1 (n1, n3, n4, n6, n7);
slice s2 (n2, n7, n5, n8, n9);
slice s3 (n6, n8, n9, n10, n11);
I need to make it flat e.g. one module in form like that:
module c17(n1, n2, n3, n4, n5, n10, n11);
input n1, n2, n3, n4, n5;
output n10, n11;
wire \s1.in3 , \s1.in2 , \s1.in1 ;
wire \s1.out2 , \s1.out1 ;
\s1.nand2 \s1.gate1 (\s1.in1 , \s1.in2 , \s1.out1 );
\s1.nand2 \s1.gate2 (\s1.in2 , \s1.in3 , \s1.out2 );
assign \s1.in1 =n1;
assign \s1.in2 =n3;
assign \s1.in3 =n4;
assign n6=\s1.out1 ;
assign n7=\s1.out2 ;
wire \s2.in3 , \s2.in2 , \s2.in1 ;
wire \s2.out2 , \s2.out1 ;
\s2.nand2 \s2.gate1 (\s2.in1 , \s2.in2 , \s2.out1 );
\s2.nand2 \s2.gate2 (\s2.in2 , \s2.in3 , \s2.out2 );
assign \s2.in1 =n2;
assign \s2.in2 =n7;
assign \s2.in3 =n5;
assign n8=\s2.out1 ;
assign n9=\s2.out2 ;
wire \s3.in3 , \s3.in2 , \s3.in1 ;
wire \s3.out2 , \s3.out1 ;
\s3.nand2 \s3.gate1 (\s3.in1 , \s3.in2 , \s3.out1 );
\s3.nand2 \s3.gate2 (\s3.in2 , \s3.in3 , \s3.out2 );
assign \s3.in1 =n6;
assign \s3.in2 =n8;
assign \s3.in3 =n9;
assign n10=\s3.out1 ;
assign n11=\s3.out2 ;
Do you know any way to do it automatically? Any free tool or maybe it even possible with Synopsys? Tell me how pls.
|Saturday, March 25th, 2006|
Hi, I wrote this code and I am wondering if it is metastable or is going to cause my design any problems if I connected the output port (qd) to the input port (d)
in summary, it's an asynchronous counter with a process that is sensitive to some input signal
each time the process is run
it reads from the input port
then writes the result to the output port
then in my design, i connected a bus from the output port to the input port.
Is that the reason for all my design problems at the moment? Because the counter's results look like this
I tried adding an LCELL before the read operation but I wasn't able to get it to work correctly and lost patience.
thanks in advance.
|Friday, March 24th, 2006|
|Wednesday, January 4th, 2006|
Hi all, I have a VHDL-newbie question and I don't know where else to turn but Livejournal!
I am making a design on Altera and my question is, if I write a VHDL using Altera Quartus II, do I need to worry about how fast the clock of the CPLD chip is running? For example, if the period of the clock is 4ns and I want to say something like:
wait for 1ns
Vout <= Vin
would that simply make a 1ns delay between Vin and Vout despite the clock speed?
thanks in advance for any help
|Wednesday, November 23rd, 2005|
"Verilog for VHDL Designers"
Does anybody have a recommendation on a Verilog book?
In particular I'm looking for something like a "Verilog for VHDL Designers" type of book, that already assumes a higher level of knowledge.
Or even a "VHDL for Verilog Designers", as I'll be able to do mental inverse transformations. :)
|Tuesday, November 15th, 2005|
VHDL for C++ programmers
I'm still trying to sort some things out in the VHDL paradigm.
Near as I can figure, a VHDL "entity" is like a C++ object prototype, a VHDL "architecture" is like a C++ object definition.
How do I instantiate something? In C++ I'd "new" an object, but I don't see a VHDL equivalent. In practice the synthesizer seems to be creating an instance of whatever object I define last. How do I instantiate more than one thing? (i.e. if I want two seperate and disjoint things to occupy the same physical device)
I'm also having trouble with packages. I'd like to put several components into a single package and "use" that, but whenever I try to do this with more than one component per package, it doesn't work. Are there any complex examples online I can look at?
|Sunday, October 16th, 2005|
Problems with Xilinx SDF Generator
I'm using the Free WebPack ISE 7.1i, and I have problems in a step of my design. I want to simulate the "Post Place & Route" circuit of my FPGA in ModelSIM, and although all the Synthesize process goes fine, at the creation of the SDF file I get:
Read and Annotate design 'driver_motor.ncd' ..
EXCEPTION:Pds:Pds_PahFileConv.c:567:1.14 - Corrupt Database
FATAL_ERROR:Anno:DesignManager.c:427:184.108.40.206 - There were DRC violations on
the original design in file driver_motor.ncd. Process will terminate. To
resolve this error, please consult the Answers Database and other online
resources at http://support.xilinx.com. If you need further assistance,
please open a Webcase by clicking on the "WebCase" link at
What should I do? I registered to 'WebCase', but I think they won't give me any solution.
|Wednesday, October 12th, 2005|
|Sunday, October 9th, 2005|
Where to get 'vcomp/vsim'?
I've read somewhere in this newsgroup that 'vcomp/vsim' are free to
download and use (at least in Linux). Where can I get them? I've googled,
and I cannot find them.
By now I've been using Sonata, but it's free version is slow, and the
Waveform displayer doesn't allow monitoring for every signal/variable.
There are restrictions.
If you've used Alliance (the french free), I'd like to know how to run the
testbench of my sources.
And if anyone uses freehdl... I'm going to give it a try. My Gentoo is
installing the latest release. 'freehdl' looks easy to use. But it
requires a VCD displayer (for the waveforms). Maybe someone can help about
that? I've found any VCD displayer in my gentoo ebuild tree.
Uf. Simulating VHDL in linux is quite difficult, I see.
No mailing list is working about FreeHDL...
I've this result when compiling a file:
$ gvhdl prova_motors_tb.vhdl *.o
gvhdl: FreeHDL root path is '/usr/share/freehdl'.
gvhdl: executing 'freehdl-v2cc -m prova_motors_tb._main_.cc -L L -o
freehdl-v2cc: v2cc-util.cc:1845: int check_for_target_type(IIR_Root*,
IIR_Type*, IIR_Expression*, RegionStack&, RuntimeCheckFlags&, bool,
std::string): Assertion `is_scalar_type(source->subtype)' failed.
gvhdl: Compilation failed!
Died at /usr/bin/gvhdl line 199.
I attach the file.( Read more...Collapse )
'bit' and 'std_logic'
In most of the examples I see that people uses std_logic instead of 'bit'
for most of the binary logic. Why? Should I avoid using 'bit'?
In most of the cases I don't specially care about 'U' states.
|Saturday, April 2nd, 2005|
I'm just thinking of buying a PCI FPGA card, so I thought I'd post in here and see if anyone has had any experience with it.
I'm thinking of a Mesa 'anything I/O' card, with a 32bit 33Mhz 3.3/5.0v PCI bus. It has a dedicated PLX 9030 chip handling the PCI side, then a Spartan II (I've never used them, they any cop?) with 200K gates and apparently a 'speed grade 5' (not sure what that means, the speed grade 6 is apparently faster so its not a ns-based rating like I'm used to). The Spartan II has 72 IO bits on three pin header type sockets..
The cost is what appeals to me - its listed at $199 for single boards. I couldn't find anything even remotely near that price with half the spec..
The card spec is at http://www.mesanet.com/pdf/parallel/5i20ds.pdf
and I'd really appreciate any comments anyone has.
PS - I also found these ( http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&category=11223&item=5763104618&rd=1&ssPageName=WD2V
) on ebay. Anyone know much about them? I couldn't find much info on them but I'm tempted to buy one anyway and then, if they are any good, buy another couple. Current Mood: sleepy
|Tuesday, March 15th, 2005|
Hello, I'm the newest member, I guess :). I just joined today! I'm a recent grad from Purdue University with a BS in Computer Engineering, and we used VHDL extensively, and basically redesigned a PIII chip (without the extent of functionality, and with a MIPS "lite" instruction set). As a student, I've written maybe 50 different similar components in VHDL. I've also worked on a VGA controller, and a Connect-4 game (hehe, I know, in VHDL it's not as fun). I cannot consider myself an expert, because Intel and AMD won't hire me, but I would consider myself to have a great interest in all aspects of embedded systems.
I hope I can contribute!!
|Friday, December 24th, 2004|
Hi there. A quick introduction - I'm Alan, I normally go by the monicker randomdude.
Like tinkering with computers, am just expanding interests towards embedded FPGA stuff. Seems pretty cool. :)
Currently I'm trying ot build a VGA interface and failing miserably. I'll post a cry for help if I cant get it working in the next few hours ;) Current Mood: sleepy
|Friday, November 26th, 2004|
Just a short intro... I'm the newest member of the vhdl_forum and I'm an ASIC engineer at Matrox Graphics, Inc. We use VHDL to design our chips. Hopefully we'll see more members in this forum in time!
Feel free to introduce yourself as well.
|Tuesday, September 28th, 2004|
need a little help
I'm teaching myself, so please forgive any dumb questions.
I've got an 8 bit counter. I want a flag to be true if the counter is below some value.
This doesn't work:
signal COUNTER : std_logic_vector(7 downto 0);
signal FLAG : std_logic;
FLAG <= COUNTER < "00110011"; -- what should go here?
|Friday, September 24th, 2004|