viric (viric) wrote in vhdl_forum,
viric
viric
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I've this result when compiling a file:
$ gvhdl prova_motors_tb.vhdl *.o
gvhdl: FreeHDL root path is '/usr/share/freehdl'.
gvhdl: executing 'freehdl-v2cc -m prova_motors_tb._main_.cc -L L   -o 
prova_motors_tb.cc prova_motors_tb.vhdl'
freehdl-v2cc: v2cc-util.cc:1845: int check_for_target_type(IIR_Root*, 
IIR_Type*, IIR_Expression*, RegionStack&, RuntimeCheckFlags&, bool, 
std::string): Assertion `is_scalar_type(source->subtype)' failed.
gvhdl: Compilation failed!
Died at /usr/bin/gvhdl line 199.


I attach the file.

library ieee ;
use ieee.std_logic_1164.all;

ENTITY prova_motors_tb is
end prova_motors_tb;

architecture testbench of prova_motors_tb is
component prova_motors
    Port ( mclk       : in std_logic;-- senyal de rellotge global
         sb_btn     : in std_logic;-- botó utilitzat com a reset
         sb_led     : out std_logic;-- sortida cap al LED de la placa D2-SB (estarà sempre a '1')
         IO4_ledg   : out std_logic;-- porta del conjunt de leds indiviuals
         IO4_btn    : in std_logic_vector(4 downto 0);-- botons de la placa DIO4
         IO4_swt    : in std_logic_vector(7 downto 0);-- interruptors de la placa DIO4
-- Utilització:
--- IO4_swt(0): PCS0n
--- IO4_swt(1): RDn
--- IO4_swt(7 downto 2): comanda
 IO4_led  : out std_logic_vector(7 downto 0);-- valor cap als LEDs de la placa DIO4.
-- s'utilitzaran per mostrar les sortides del sistema
         IO4_an     : out std_logic_vector(3 downto 0);-- Ã node dels displays de set segments
         IO4_ssg    : out std_logic_vector(6 downto 0);-- valor cap als displays de set segments. Sortirà el valor
-- de la comanda i dels senyals d'habilitació
    IO4_ssgdp  : out std_logic);-- punt decimal dels displays de set segments
end component;

    constant period: time := 20 ns ; -- 50MHz
    signal done : boolean := false;
    
    -- per a saber a quin cicle estem a la simulació
    signal Cycle : NATURAL := 0 ;
    
    signal clk, sb_led, IO4_ledg, IO4_ssgdp : std_logic := '0';
    signal reset : std_logic := '1'; -- perque comenci bé el reset
    signal IO4_btn : std_logic_vector(4 downto 0) := "00000";
    signal IO4_swt : std_logic_vector(7 downto 0) := "00000011";
    alias PCS0n: std_logic is IO4_swt(0);
    alias RDn: std_logic is IO4_swt(1);
    alias Comanda: std_logic_vector(5 downto 0) is IO4_swt(7 downto 2);
    signal IO4_led : std_logic_vector(7 downto 0) := "00000000";
    signal IO4_an : std_logic_vector(3 downto 0) := "0000";
    signal IO4_ssg : std_logic_vector(6 downto 0) := "0000000";

    
begin
xip: prova_motors
port map(
mclk => clk,
sb_btn => reset,
sb_led => sb_led,
IO4_ledg => IO4_ledg,
IO4_btn => IO4_btn,
IO4_swt => IO4_swt,
IO4_led => IO4_led,
IO4_an => IO4_an,
IO4_ssg => IO4_ssg,
IO4_ssgdp => IO4_ssgdp);

    -- Rellotge. Controla: clk, Cycle
    ClkProcess: PROCESS(done, clk)
    BEGIN
IF (not done) THEN
    IF (clk = '1') THEN
Cycle <= Cycle + 1 ;
    END IF ;
    clk <= NOT clk after period / 2 ;
END IF ;
    END PROCESS ClkProcess;
    
test: process
begin
wait until clk = '0';
reset <= '1';
wait for period * 1;
reset <= '0';
wait for period * 1;
Comanda <= "111000";
PCS0n <= '0';
RDn <= '1';
wait for period * 1;
PCS0n <= '1';
RDn <= '0';
wait for period * 12000;
done <= true;
wait;
end process test;

end testbench;

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