Near as I can figure, a VHDL "entity" is like a C++ object prototype, a VHDL "architecture" is like a C++ object definition.
How do I instantiate something? In C++ I'd "new" an object, but I don't see a VHDL equivalent. In practice the synthesizer seems to be creating an instance of whatever object I define last. How do I instantiate more than one thing? (i.e. if I want two seperate and disjoint things to occupy the same physical device)
I'm also having trouble with packages. I'd like to put several components into a single package and "use" that, but whenever I try to do this with more than one component per package, it doesn't work. Are there any complex examples online I can look at?