Ромка (obrut_mra) wrote in vhdl_forum,
Ромка
obrut_mra
vhdl_forum

Flat verilog netlist

May be it's a dumb question but ... =)
I have a hierarchical Verilog, something like that:
module slice (in1, in2, in3, out1, out2);
   input in1, in2, in3;
   output out1, out2;
   nand2 gate1 (in1, in2, out1);
   nand2 gate2 (in2, in3, out2);
endmodule

module c17 (n1, n2, n3, n4, n5, n10, n11 );
   input n1, n2, n3, n4, n5;
   output n10, n11;
   slice s1 (n1, n3, n4, n6, n7);
   slice s2 (n2, n7, n5, n8, n9);
   slice s3 (n6, n8, n9, n10, n11);
endmodule
I need to make it flat e.g. one module in form like that:
module c17(n1, n2, n3, n4, n5, n10, n11);
  input  n1, n2, n3, n4, n5;
  output  n10, n11;
  wire n6;
  wire n7;
  wire \s1.in3 , \s1.in2 , \s1.in1 ;
  wire \s1.out2 , \s1.out1 ;
  \s1.nand2  \s1.gate1 (\s1.in1 , \s1.in2 , \s1.out1 );
  \s1.nand2  \s1.gate2 (\s1.in2 , \s1.in3 , \s1.out2 );
  assign \s1.in1 =n1;
  assign \s1.in2 =n3;
  assign \s1.in3 =n4;
  assign n6=\s1.out1 ;
  assign n7=\s1.out2 ;
  wire n8;
  wire n9;
  wire \s2.in3 , \s2.in2 , \s2.in1 ;
  wire \s2.out2 , \s2.out1 ;
  \s2.nand2  \s2.gate1 (\s2.in1 , \s2.in2 , \s2.out1 );
  \s2.nand2  \s2.gate2 (\s2.in2 , \s2.in3 , \s2.out2 );
  assign \s2.in1 =n2;
  assign \s2.in2 =n7;
  assign \s2.in3 =n5;
  assign n8=\s2.out1 ;
  assign n9=\s2.out2 ;
  wire \s3.in3 , \s3.in2 , \s3.in1 ;
  wire \s3.out2 , \s3.out1 ;
  \s3.nand2  \s3.gate1 (\s3.in1 , \s3.in2 , \s3.out1 );
  \s3.nand2  \s3.gate2 (\s3.in2 , \s3.in3 , \s3.out2 );
  assign \s3.in1 =n6;
  assign \s3.in2 =n8;
  assign \s3.in3 =n9;
  assign n10=\s3.out1 ;
  assign n11=\s3.out2 ;
endmodule
Do you know any way to do it automatically? Any free tool or maybe it even possible with Synopsys? Tell me how pls.
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